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FO-WLP : Fan Out Wafer Level Package
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Assembly and Test, Bumping, 주문형, 포장 반도체 생산, 조립, 검사, 임가공, 화상이미지 전송 칩 제작

연락처
041-520-6400
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gyuho.lee@sfasemicon.com
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SKU
35727
제품명
FO-WLP : Fan Out Wafer Level Package
모델명
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사이즈
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제품 상세 정보

Description

On a semiconductor chip after RDL.
Fan-out structure : Some of solder balls are attached to a substrate outside of a semiconductor chip after RDL.
The process of molding the molding compound resin should be performed for Re-distribution layer which is expanded outside of chip. Additional processes for molded layer requires and turn around time is increased. The fan-out package with EMC is consequently warped due to big CTE difference after molding and package crack is generated at the interface among four different materials (Passivation, EMC Cu and Die)

 

Application

ㆍMobile phones (highest volume application)

ㆍDigital cameras and camcorders

ㆍMP3 players / Watch modules

ㆍLaptop and tablet computers / Medical

ㆍAutomotive

ㆍWearable electronics

 

Feature

ㆍReduction of TAT time with skipping WSS process.

ㆍMFG cost down & warpage improvement through using low cure polymer

ㆍNo EMC resin particle issue at sputtering process

ㆍImproved lithography techniques to compensate die shift generated at die mount process

ㆍHigh reliability performance of large sized FO-WLP

(주)에스에프에이반도체
(주)에스에프에이반도체
Assembly and Test, Bumping, 주문형, 포장 반도체 생산, 조립, 검사, 임가공, 화상이미지 전송 칩 제작
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